1. Technical Field
The present disclosure relates generally to semiconductor structure design and fabrication and, more particularly, to a semiconductor structure with self-aligned device contacts and a method of forming the semiconductor structure.
2. Description of the Related Art
As device densities within semiconductor structures increase, overlay tolerances between contact (e.g., source/drain contact) and gate lithography levels are difficult to achieve. As a result source/drain contact sizes are reduced (i.e., the contact diameter is scaled) to ensure that the contacts do not short the source/drain diffusion region to the gate electrode. In particular, reducing the contact sizes avoids forming the contacts through the gate sidewall spacers and, thereby, contacting unsilicided active silicon (e.g., a source/drain extension) and severely degrading external resistance. However, scaling the contact size substantially increases the resistance of the contact. Therefore, there is a need in the art for a semiconductor structure with a device contact that provides optimal resistance without impacting device yield.